Samsung Electronics is signaling a fundamental shift in semiconductor strategy as the traditional approach of shrinking transistors delivers diminishing returns, according to recent industry reports. The company’s Foundry Vice President Shin Jong-shin reportedly revealed that process miniaturization alone now offers only 10-15% improvements in performance and area reduction.
Table of Contents
The DTCO Revolution
Speaking at the eighth Semiconductor Industry-Academia-Research Exchange Workshop in Seoul, Shin indicated that the industry has shifted toward Design-Technology Co-Optimization (DTCO) as physical scaling becomes increasingly challenging. Both Samsung and its rival TSMC have reportedly established dedicated DTCO teams to pursue simultaneous design and process improvements.
“As process performance improvement reaches its limits, the industry is paying attention to DTCO,” Shin stated, according to coverage from The Elec. The significance of this approach is growing rapidly—while DTCO contributed approximately 10% of overall performance improvement at 7nm, that share is expected to reach 50% at 3nm and below.
Beyond Traditional Scaling
What exactly does DTCO involve? Sources describe it as a methodology where engineers review existing process constraints while exploring alternatives based on designer requests. By modifying these processes, cells can be placed more efficiently and surface area reduced, delivering benefits beyond what pure node shrinkage can accomplish.
The timing of this strategic emphasis is particularly noteworthy. Samsung has already transitioned from FinFET architecture to Gate-All-Around (GAA) structures starting with its 3nm process. While the 3nm GAA implementation reportedly struggled with yield issues, the company’s 2nm node is showing significant promise according to industry observers.
Shin put the semiconductor improvement trajectory in perspective by contrasting it with AI development. “Unlike the artificial intelligence field where performance doubles every few months, in the world of semiconductor processing, even a 1-2% difference is very important,” he noted. That seemingly small performance margin can become the deciding factor in process selection for major clients.
Broader Optimization Strategy
Samsung’s approach appears to be expanding beyond DTCO to encompass even more comprehensive optimization frameworks. Company executives reportedly indicated that DTCO will evolve into System-Process Co-Optimization (SPCO) and System-Design-Process Co-Optimization (SDTCO), creating a more holistic approach to semiconductor advancement.
Meanwhile, the company is leveraging AI in an attempt to automatically create new cell structures that achieve smaller area and reduced power consumption. This represents another dimension of the optimization strategy—using artificial intelligence to discover design configurations that human engineers might overlook.
Strategic Implications
The renewed focus on optimization rather than pure node advancement may explain Samsung’s recent roadmap decisions. Industry analysts suggest the Korean foundry has reportedly completed basic design of its second-generation 2nm GAA process, with a third iteration expected within two years.
This DTCO emphasis might also factor into Samsung’s apparent decision to delay its 1.4nm node in favor of improving current processes. Rather than competing head-on with TSMC in the race to the smallest node, Samsung appears to be prioritizing performance and efficiency gains through smarter design-process integration.
The semiconductor industry’s pivot toward co-optimization strategies represents a recognition that the golden era of straightforward node scaling has ended. As physical limitations become more pronounced, companies like Samsung and TSMC are increasingly competing on their ability to extract maximum performance through intelligent design-technology partnerships rather than simply chasing smaller feature sizes.
